View MB40168_141070.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28501-2E
ASSP
Single Chip 8-Bit A/D and 9-Bit D/A Converter
MB40168/MB40178
s DESCRIPTION
The Fujitsu MB40168 and MB40178 are high speed, low power single chip A/D and D/A converters designed for video processing applications. The A/D converter has a resolution of 8 bits while the D/A converter has 9bit resolution. They are fabricated in Fujitsu's advanced bipolar technology, and housed in a 48-pin plastic shrink DIP or 44-pin plastic QFP package.
s FEATURES
* Resolution * * * * * A/D: 8 bits D/A: 9 bits Conversion Rate A/D: Max. 20 MSPS D/A: Max. 40 MSPS Linearity Error A/D: Max. + 0.3% D/A: Max. + 0.2% On-chip reference voltage generator (resistor divided method) and clamp circuit Analog Input Voltage 3 to 5 V without clamp circuit 0 to 3 V in 1.95 VP-P clamp circuit Analog Output Voltage 3 to 5 V
(Continued)
s PACKAGES
48 pin, Plastic SH-DIP 44 pin, Plastic QFP
(DIP-48P-M01)
(FPT-44P-M11)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB40168/MB40178
(Continued) * Digital Input/Output Interface * Power Supply Voltage * Power Dissipation * Package Options
TTL Levels + 5.0 V single power supply Typ. 350 mW 48-pin Plastic Shrink DIP/ 44-pin Plastic QFP Package
s PIN ASSIGNMENTS
* MB40168
(TOP VIEW)
D.GND (TOP VIEW) DACLK D D9 (LSB) (LSB) D D9 DACLK D.GND D.GND A.GND A.OUT COMP V CCD D D8 D D7 D D6 D D6 D D5 D D4 D D3 D D2 (MSB) D D1 (LSB) D A8 D A7 D A6 D A5 D A4 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 (MSB) D A1 D.GND D A3 D A2 V RT A.GND A.GND V CCD ADCLK V CCA V INC V RIN V REF V RB D.GND A.GND V CCD V CCA V RM V INA V CLMP V OUTC D D5 D D4 D D3 D D2 (MSB) D D1 NC NC NC (LSB) D A8 D A7 D A6 D A5 D A4 D A3 D A2 (FPT-44P-M11) (MSB) D A1 ADCLK D.GND VCCA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A.GND V CCD V CCA A.OUT COMP V RIN V REF V RB NC D.GND A.GND V CCD V CCD V CCA V CCA V RM V INA V CLMP V OUTC V INC V RT V CCA V CCD A.GND
D D7
D D8
(DIP-48P-M01)
2
MB40168/MB40178
* MB40178
(TOP VIEW)
D.GND (TOP VIEW) DACLK D D1 (MSB) (MSB) D D1 DACLK D.GND D.GND A.GND A.OUT COMP V CCD D D2 D D3 D D4 D D4 D D5 D D6 D D7 D D8 (LSB) D D9 (LSB) D A8 D A7 D A6 D A5 D A4 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 (MSB) D A1 D.GND A.GND A.GND V CCD V CCA ADCLK V INC V RT D A3 D A2 V RIN V REF V RB D.GND A.GND V CCD V CCA V RM V INA V CLMP V OUTC D D5 D D6 D D7 D D8 (LSB) D D9 NC NC NC (LSB) D A8 D A7 D A6 D A5 D A4 D A3 D A2 (FPT-44P-M11) (MSB) D A1 ADCLK D.GND VCCA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A.GND V CCD V CCA A.OUT COMP V RIN V REF V RB NC D.GND A.GND V CCD V CCD V CCA V CCA V RM V INA V CLMP V OUTC V INC V RT V CCA V CCD A.GND
D D3
D D2
(DIP-48P-M01)
3
MB40168/MB40178
s PIN DESCRIPTION
Symbol VCCD VCCA DGND AGND DA8 - DA1 ADCLK VRT VINC Pin No. QFP-44 19, 28, 37 20, 27, 36 16, 30, 39, 40 17, 18, 29, 38 7 - 14 15 21 22 SH-DIP-48 26, 36, 37, 47 27, 34, 35, 46 1, 24, 39 25, 38, 48 15 - 22 23 28 29 I/O -- -- -- -- O I I I Name & Function Digital Power Supply pins (+ 5 V). Analog Power Supply pins (+ 5 V). Digital Ground (0 V). These pins should be connected to the analog ground on the application system. Analog Ground (0 V). These pins should be connected to the analog ground on the application system. ADC Digital Output pins. TTL level. ADC Clock Input pin. TTL level. ADC Reference Voltage Input pin. (5 V Input) Sync Tip Clamp Circuit Analog Input pin. (0 - 3 V, 1.95 VP-P). When a clamp circuit is not used, this pin is connected to ground. Clamp Circuit Analog Output pin. It is used by adding a capacitor (1 F or more) between VCLMP and VOVTC pins. When a clamp circuit is not used, this pin is left open. Clamp Voltage Output pin (3.05V Output). When a clamp circuit is not used, this pin is left open. ADC Analog Signal Input pin. (3 - 5 V) ADC Middle Reference Voltage Monitor pin. (Mid of VRT - VRB is set to this pin). Normally this pin is left open. ADC Reference Voltage Input pin. (3 V) Reference Voltage Output pin. (Resistor Divider, 3 V) By connecting this pin to VRB pin, 3V Voltages are generated. When a reference voltage is not used, this pin is left open. DAC Reference Voltage Input pin (3 V) Phase Compensation Capacitor pin. (Capacitor greater than 0.1 F should be connected between this pin and Analog Ground.) Analog Signal Output pin DAC Clock Input pin. TTL level. DAC Digital Data Input pins. TTL level.
VOUTC VCLMP VINA VRM VRB VREF VRIN COMP AOUT DACLK DD9 - DD1
23 24 25 26 31 32 33 34 35 41 1 - 6 *1 42 - 44
30 31 32 33 41 42 43 44 45 2 3 - 11*2
O O I -- I O I -- O I I
*1: MB40168 (MSB: 6 pin, LSB: 42 pin), MB40178 (MSB: 42 pin, LSB: 6 pin) *2: MB40168 (MSB: 11 pin, LSB: 3 pin), MB40178 (MSB: 3 pin, LSB: 11 pin)
4
MB40168/MB40178
s BLOCKDIAGRAM
VCCD VCCA
VINA
ADCLK VRT
R1 R
1
DA1 (MSB)
2
DA2 R R/2 VRM R/2
128
127
DA3 255 to 8 Encoder Latch & Buffer DA4 DA5 DA6
R R
DA7
254
DA8 (LSB)
255
R2
VRB VINC VOUTC 0.6VCCA + 50mV VCLMP 0.6VCCA VREF VRIN Reference resistor Amp COMP Reference voltage generator
Clamp
DACLK DD9 (LSB) 9 DD1 (MSB) Input buffer 9
Master Slave register
9
Buffer
9
Current switch
9
R-2R Ladder resistor network
AOUT
DGND
AGND
5
MB40168/MB40178
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Analog input voltage Reference voltage Clamp circuit input voltage Digital input voltage Storage temperature Symbol VCCA, VCCD VINA VRT, VRB, VRIN VINC VIND TSTG Rating -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -0.5 to 7.0 -55 to +125 Unit V V V V V C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6
MB40168/MB40178
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage *1 Clamp circuit input voltage *2 Analog input voltage
Top
Symbol VCCA, VCCD VINC VINA VRT VRB VCCA - VRIN
Value Min. 4.75 0 VRB VCCA - 0.1 2.75 0.7 2.65 2.0 -- -400 -- -- -- 22.5 10.5 22.5 10.5 10 4 1 0.1 -20 Typ. 5.00 -- -- VCCA 3.0 2.0 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.25 3 VRT VCCA + 0.1 3.25 2.2 4.3 -- 0.8 -- 1.6 20 40 -- -- -- -- -- -- -- -- +70
Unit V V V V V V V V V A mA MHz MHz ns ns ns ns ns ns F F
o
ADC reference voltage *3
Bottom
DAC reference voltage Digital input high voltage Digital input low voltage Digital output high current Digital output low current
A/D
VRIN
VIHD VILD IOH IOL fCLKAD fCLKDA tWHAD tWHDA tWLAD tWLAD tSU tH CCLMP CCOMP Ta
Clock frequency
D/A A/D D/A A/D D/A
Minimum high clock pulse width Minimum Low clock pulse width Set up time Hold time Clamp capacitance Phase compensation capacitance Ambient operating temperature
C
*1: VCCA and VCCD must be used in the same voltage level. *2: VINC must have an amplitude of VRT - VCLMP. *3: VRT - VRB must have 2.0V0.1V.
7
MB40168/MB40178
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
* Analog Block (VCCA = VCCD = 4.75 V to 5.25 V, Ta = -20 oC to +70 oC) Parameter ADC resolution DAC resolution ADC linearity error DAC linearity error Analog input equivalent impedance Analog input capacitance Analog input high current Analog input low current Reference output voltage Clamp voltage ADC reference current DAC reference current Clamp circuit input current Full scale output voltage Zero scale output voltage Output impedance Supply current Symbol -- -- LEAD LEDA RINA CINA IIHA IILA VREF VCLMP IRB IRIN IINC VOFS VOZS RO ICC Condition -- -- DC accuracy VCCA = VCCD = 5.0 V RINA = VRT -VRB IIHA - IILA Value Min. -- -- -- -- 0.3 -- -- -- 0.6VCCA - 0.1 -- -8.5 -- -600 VCCA-20mV 2.934 192 -- Typ. 8 9 0.15 0.1 1.3 40 -- -- 0.6VCCA VREF + 50 mV -5.5 -- -200 VCCA 3.004 240 70 Max. -- -- 0.3 0.2 -- -- 45 40 0.6VCCA+ 0.1 -- -3.0 10 -- -- 3.072 288 125 Unit bits bits % % M pF A A V V mA A A V V mA
fINA = 1 MHz VINA = VRT VINA = VRB VREF, VRB, VRIN shorted together -- -- VRIN = 3.000 V VINC = 0 V -- VCCA = 5.00 V VCCD = 5.00 V VRIN = 3.000 V Ta = +25 oC --
8
MB40168/MB40178
* Digital Block (VCCA = VCCD = 4.75 V to 5.25 V, Ta = -20 oC to +70 oC) Parameter Digital output high voltage Digital output low voltage Digital input high voltage Digital input low voltage Digital input high current Digital input low curent Symbol VOHD VOLD VIHD VILD IIHD IILD Condition IOH = -400 A IOL = 1.6 mA -- -- VIHD = 2.7 V VILD = 0.4 V Value Min. 2.7 -- 2.0 -- -- -100 Typ. -- -- -- -- -- -- Max. -- 0.4 -- 0.8 20 -- Unit V V V V A A
2. AC CHARACTERISTICS
(VCCA = VCCD = 4.75 V to 5.25 V, Ta = -20 oC to +70 oC) Parameter Maximum conversion rate Digital output delay time Analog output delay time Analog output rise time Analog output fall time Settling time A/D D/A Symbol fSAD fSDA tpd AD tpd DA tr tf tset LH, tset HL Condition -- -- -- CL = 15 pF Terminating resistor AOUT = 240 Value Min. 20 40 8 -- -- -- -- Typ. -- -- 15 10 5 5 16 Max. -- -- 30 -- -- -- -- Unit MSPS MSPS ns ns ns ns ns
9
MB40168/MB40178
s LINEARITY ERROR OF A/D CONVERSION
* Ideal Characteristic
Step 255 254 253 * * * 129 128 127 * * * 2 1 0 Output Code 11111111 11111110 11111101 * * * 10000001 10000000 01111111 * * * 00000010 00000001 00000000 VZT 3.006V VFT 4.996V
VINA
Note: The values for VZT and VFT are typical values under conditions that VCCA = VCCD = VRT = 5.000V and VRB = 3.000V.
* Actual Characteristic
Step 255 254 253 * * * 129 128 127 * * * 2 1 0 Output Code 11111111 11111110 11111101 * * * 10000001 10000000 01111111 * * * 00000010 00000001 00000000 VZT LE1 VINA VFT LE2 LE129 LE128 LE127
LE253
10
MB40168/MB40178
s OUTPUT VOLTAGE CHARACTERISTIC OF D/A CONVERTER BLOCK
Input DD1 ~ DD9 511 (VCCA) VOFS
Output A.OUT 5.000V 5.000V
0
VOZS (VRIN)
3.004V 3.000V 1 LSB = 4mV
s CALCULATION OF DAC OUTPUT VOLTAGE WHEN THE IDEAL CONVERSION IS PERFORMED
511-N 512 x (VCCA - VRIN)
AOUTN = VCCA -
(N: Digital code (0 ~ 511) VOFS = VCCA VOZS = VCCA - 512 x (VCCA - VRIN)
511
11
MB40168/MB40178
s EQUIVALENT CIRCUITS OF ADC BLOCK
* Analog Input Equivalent Circuit
VCCA
VCCA VD
VINA
VINA CINA IBIAS RINA
A.GND
A.GND x 255 circuits
A.GND
VRB
CINA: Junction Capacitance of non-linear emitter follower RINA: Linear resistance model of input current by the comparator switching VINA < VRB: CLK = "H": VRB: This is the voltage on VRB Pin, not VRB Pin itself. IBIAS: Constant input bias current VD: Base-Collector junction diode of emitter follower transistor
* Clamp Input Equivalent Circuit
VCCA
2.0mA
0.6 x VCC + 50mV +VBE
VINC
850k
A.GND
VOUTC -+ CCLMP
VCLMP
12
MB40168/MB40178
* Digital Input Equivalent Circuit
VCCD 50k 6.5k 50k
3.2k
3.2k
Clock Input ADCLK
VTH = 1.4V
D.GND
* Digital Output Load Circuit
To pin tested
Test point
CL = 15pF
D.GND
NOTE:
CL includes the floating capacitance of probe and jig.
13
MB40168/MB40178
s EQUIVALENT CIRCUITS OF DAC BLOCK
* Digital Input Equivalent Circuit
VCCD 50k 50k
Digital Input D01 - D09 DACLK
VTH = 1.4V
D.GND
* Analog Output Equivalent Circuit
VCCA RO = 240 A.OUT IO A.GND
* Reference Voltage Generator Equivalent Circuit
VCCA 20k Buffer VREF 30k A.GND IRB
14
MB40168/MB40178
s TYPICAL CONNECTION CIRCUITS
Example 1: Video Signal Input to VINC Pin
+5V +5V
VCCA Video Signal Input VINC
VCCD
VOUTC + VCLMP MB40168/MB40178
1 F
VINA
AGND
DGND
Example 2: Video Signal Input to VCLMP and VINA Pins
+5V +5V
VCCA VINC
VCCD
+9V External Circuit
VOUTC MB40168/MB40178 VCLMP
2.2 k 1 F + Video Signal Input 2SA933 AGND DGND
VINA
AGND
15
MB40168/MB40178
s CLAMP CIRCUIT OPERATION
Clamp Circuit
Clamp Voltage is set at 0.6 x VCC + 50 mV (typ.) VCCA VCCA
I 2 mA Bias Circuit
VINC
AGND VOUTC 3.05 V
CCLMP + VCLMP
VINA
A/D Converter
Signal Level at VINA pin Signal Level at VINC pin VCCA = 5.0 V
AGND
VCLMP 3.05 V VREF 3.0 V
Note: When Clamp Circuit is not applied the signals should be connected as follows: VINC: Connect to GND. VOUTC: Leave open. VCLMP: Leave open.
16
MB40168/MB40178
s TYPICAL CONNECTION CIRCUIT(Example)
System Analog Ground DAC Clock Input 1 2 3 4 5 Digiral Input (DAC) 6 7 8 9 DGND DACLK (LSB) DD9 DD8 DD7 DD6 DD5 DD4 DD3 AGND 48 VCCD 47 VCCA 46 AOUT 45 COMP 44 VRIN 43 VREF 42 0.1 F VRB 41 NC 40 DGND 39 0.1 F System Analog Power Supply Analog O/P (DAC)
0.1 F
10 DD2 11 (MSB) DD1 Open Open Open 12 NC 13 NC 14 NC 15 (LSB) DA8 16 DA7 Digiral Output (DAC) 17 DA6 18 DA5 19 DA4 20 DA3 21 DA2 ADC Clock Input 22 (MSB) DA1 23 ADCLK 24 DGND
MB40168
AGND 38 VCCD 37 VCCD 36 2 F VCCA 35 VCCA 34 VRM 33 VINA 32 VCLMP 31 VOUTC 30 VINC 29 VRT 28 VCCA 27 1 F VCCD 26 AGND 25 Analog Input (ADC) 1 F Open
17
MB40168/MB40178
s NOTES ON PCB LAYOUT
Power Supply Lines
The device's power supply lines (VCCA, VCCD, AGND and DGND) should be laid out as analog lines and should be separated in so far as possible from other digital lines in order to reduce noise. Also the track widths of these lines should be as wide as possible to reduce parasitic impedance.
Coupling Capacitors
The device's power supply lines VCCA and VCCD and the reference voltage pins VRIN, VREF, VRB, and VRT should be decoupled to analog ground by means of approx. 1 F capacitors which should be placed as close as possible to these pins.
Digital Output Load
The load at the digital outputs should be kept as low as possible to prevent noise in the power supply lines caused by digital output switching. If, due to long wiring, the load becomes large then a buffer with small input capacitance should be inserted to reduce load capacitance.
s OTHER NOTES ON OPERATION
When using the D/A converter with its VRIN pin connected to the VREF pin, the A/D converter's VRB pin must also be connected to the VREF because otherwise the internal reference voltage generation circuitry cannot output 3 V. When using the D/A converter with 8 bit resolution the DD9 (LSB) pin should be grounded.
18
MB40168/MB40178
s PACKAGE DIMENSIONS
48 pin, Plastic SH-DIP (DIP-48P-M01)
43.69 -0.30 +.008 1.720 -.012
+0.20
INDEX-1 13.800.25 (.543.010) INDEX-2
5.25(.207) MAX 3.00(.118) MIN
+0.50
0.51(.020)MIN 0.250.05 (.010.002)
1.00 -0 +.020 .039 -0 1.7780.18 (.070.007) 1.778(.070) MAX
0.450.10 (.018.004)
15.24(.600) TYP
15MAX
40.894(1.610)REF
C
1994 FUJITSU LIMITED D48002S-3C-3
Dimensions in mm (inches).
(Continued)
19
MB40168/MB40178
44 pin, Plastic QFP (FPT-44P-M11)
14.400.40 SQ (.567.016) 10.000.20 SQ (.394.008)
33 23
2.35(.093)MAX 0.05(.002)MIN (STAND OFF)
Details of "A" part
34 22
0.15(.006)
INDEX
8.00 (.315) REF
11.600.30 (.457.012)
0.20(.008) 0.18(.007)MAX 0.53(.021)MAX
44
"A"
12
Details of "B" part LEAD No.
1 11
0.80(.0315)TYP
0.300.10 (.012.004) "B"
0.16(.006)
M
0.150.05 (.006.002) 0~10 1.400.30 (.055.012)
0.10(.004)
C
1994 FUJITSU LIMITED F44018S-1C-1
Dimensions in mm (inch).
20
MB40168/MB40178
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED
Printed in Japan
24

▲Up To Search▲

Price & Availability of MB40168

	To Download MB40168 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .